The present invention relates to a semiconductor storage device and a method of manufacturing the same. More particularly, the present invention relates to an electrode construction for a capacitor section in a cell of a ferroelectric memory and that of a high dielectric memory.
In recent years, dynamic random access memory (DRAM) cells each constructed of one MOS (metal oxide film semiconductor) transistor and one capacitor are mainly manufactured. With demands for high integration and fine processability in recent years, it has become more and more difficult to secure the capacity of a cell in the DRAMs having such a construction. Therefore, generally, efforts are made to develop methods of increasing the area of an electrode to secure the cell capacity.
Increasing the area of the electrode to secure the capacity of the cell is realized by constructing the electrode in a three-dimensional structure. However, because this method causes the manufacturing process to be very complicated, attempts to increase the area of the electrode by this method have almost reached the limit. Therefore, if a circuit integration further progresses, it will be difficult to secure the capacity of the cell using this method. Further, attempts to make dielectrics thinner have almost reached the limit, too. Therefore, in order to secure the cell capacity, researches are being made to develop new methods of using an oxide having a high dielectric constant (hereinafter referred to as "high dielectric") such as (Ba.sub.x Sr.sub.1-x) TiO.sub.3 (0.ltoreq.x.ltoreq.1) as a dielectric material.
In the meantime, with the progress of a thin film-forming technique, ferroelectric non-volatile memories (FeRAM) operating at a high density and speed are being developed by combining the thin film-forming technique and a semiconductor memory-fabricating technique with each other.
The researches of such ferroelectric non-volatile memories are energetically made for practical application because it is considered that due to their properties of high-speed write/read, operations at low voltages, and resistance to repeated write/read operations, the ferroelectric non-volatile memories will be able to replace not only the conventional non-volatile memories such as EPROMs (Erasable Programmable ROMs), EEPROMs (Electrically Erasable ROMs), and flash memories, but also SRAMs (static RAMs) and DRAMs (Dynamic RAMs).
the following substances have been investigated as a ferroelectric substance to be used in a capacitor section of such a non-volatile memory: PbZr.sub.x Ti.sub.1-x O.sub.3 (0.ltoreq.x.ltoreq.1) (hereinafter referred to as "PZT"), and SrBi.sub.2 Ta.sub.2 O.sub.9 and Bi.sub.4 Ti.sub.3 O.sub.12 which each have fatigue characteristics more favorable than the PZT and can be driven at low voltages.
However, in order to allow these ferroelectrics and the high dielectrics to display their characteristics fully, it is necessary to heat-treat them in an oxidizing atmosphere at a temperature of as high as 400.degree. C.-800.degree. C.
When forming a highly integrated DRAM or FeRAM having a stack construction by using the ferroelectric or high dielectric material, generally, a plug formed of polysilicon or the like is used to electrically connect a CMOS (complementary metal oxide semiconductor) section and a capacitor with each other. FIG. 17 shows an example of such a construction. Reference numeral 5 in FIG. 17 denotes a plug. A lower electrode 10 of the capacitor is formed of platinum (Pt) having a high degree of resistance to an oxidation reaction in forming a film at high temperatures.
In this case, it is necessary to form a barrier metal 11 made of a nitrided metal such as titanium nitride (TiN) between the lower electrode 10 of the capacitor and the plug 5. The barrier metal 11 serves to prevent Pt of the lower electrode 10 and polysilicon of the plug 5 from reacting with each other and also to prevent elements composing a ferroelectric film 8 (or a high dielectric film) from diffusing through the lower electrode 10 to the CMOS section in a heat-treating process.
In FIG. 17, reference numeral 1 denotes a silicon substrate, reference numeral 2 denotes a gate electrode, reference numeral 3 denotes a source region, reference numeral 4 denotes a drain region, reference numeral 6 denotes a LOCOS (LOCal Oxidation of Silicon) oxide film, reference numerals 7 and 9 denote interlaminar insulation films, and reference numeral 12 denotes an upper electrode of the capacitor section.
However, the semiconductor storage device having the CMOS section and the capacitor section electrically connected by the plug 5 as shown in FIG. 17 has the following problems:
That is, it is necessary that the barrier metal 11 has a thickness of about 2000 .ANG. to prevent the elements of the ferroelectric film 8 from diffusing into other films in a heat-treating process. Consequently, the total of the thickness of the barrier metal 11 and that (1000 .ANG.) of the lower electrode 10 is about 3000 .ANG.. Therefore, the total thickness of the capacitor section including the thickness of the dielectric substance 8 is very great, so that there is necessarily a big difference in level, or unevenness, in the capacitor section.
Therefore, in forming a contact hole in the interlaminar insulation film 9 and forming metal wiring after the interlaminar insulation film 9 is formed, errors occur due to a great difference in level, or unevenness, of the capacitor in a photolithographic process used for the fine processing. Thus, materials cannot be processed submicroscopically.
Further, in the case of the barrier metal 11 formed of TiN, as described above, Tin is easily oxidized by oxygen included in an atmosphere and permeating through Pt of the lower electrode 10 during the heat=treatment of the ferroelectric substance 8 (or a high dielectric). Consequently, a volume change and a film stress occur, which results in separation of the TiN (barrier metal 11) from the Pt (lower electrode 10) and which will cause hillocks and cracks in the Pt (lower electrode 10).